1. Field of the Invention
Embodiments of the invention relate to a polymer resin composition that may be used in fabricating a semiconductor device, a method for forming a pattern using the polymer resin composition, and a method for fabricating a capacitor using the polymer resin composition. In particular, embodiments of the invention relate to a polymer resin composition comprising a copolymer, a thermal acid generator, a cross-linking agent, and a photoacid generator; a method for forming a blocking pattern using the polymer resin composition; and a method for fabricating a capacitor using the polymer resin composition.
This application claims priority to Korean Patent Application No. 2006-35205, filed on Apr. 19, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
In a semiconductor device such as a dynamic random access memory (DRAM) device, a capacitor generally includes a lower electrode, a dielectric layer, and an upper electrode. In addition, the capacitance of a memory device having such a capacitor may be improved by increasing an electrostatic capacitance of the capacitor.
As the degree of integration of DRAM devices has increased to the point where a DRAM device may have a gigabyte of data storage capacity, the area in the device occupied by a single unit cell has been gradually reduced. In order to improve the capacitance of capacitors, the structure of individual capacitors has been changed from a plane type structure to a box type structure or a cylindrical type structure. The box type structure and the cylindrical type structure each have a high aspect ratio.
A cylindrical capacitor includes a lower electrode having a cylindrical shape. The cylindrical lower electrode is generally formed using a mold layer pattern and a blocking pattern that fills an opening in the mold layer pattern. The blocking pattern is formed from an oxide or a photoresist.
In a method for forming the cylindrical lower electrode using a mold layer pattern and a blocking pattern including an oxide, an etch stop layer and a mold layer are sequentially formed on a substrate on which a contact plug has been formed. The etch stop layer is formed from a nitride and the mold layer is formed from an oxide. After a photoresist pattern is formed on the mold layer, an opening exposing the contact plug is formed through an etching process to form a mold layer pattern on the substrate. The photoresist pattern is then removed through an ashing process and a cleaning process.
A conductive layer from which a lower electrode will be formed is formed on the exposed contact plug, the opening, and the mold layer pattern. The opening is then filled with an oxide to form a blocking layer on the conductive layer. Thereafter, upper portions of the blocking layer and the conductive layer are removed by performing a chemical mechanical polishing (CMP) process or an etch-back process. As a result, a lower electrode having a cylindrical shape is formed on the substrate, and a blocking pattern filling the opening is subsequently formed.
The blocking pattern filling the opening and the mold layer pattern are then removed through a wet etching process to thereby expose inner and outer sidewalls (i.e., both sidewalls) of the cylindrical lower electrode.
However, there are multiple drawbacks to the method described above for forming the cylindrical capacitor.
For example, in the method described above, it takes a relatively long time to deposit an oxide, which, in the method described above, is a necessary step in forming the cylindrical capacitor along with partially removing the oxide using an etch-back process or a CMP process. Thus, overall manufacturing productivity may be relatively low.
In addition, the opening to be filled with the oxide has a very narrow width and a relatively high aspect ratio, so it may be difficult to deposit the oxide used as a blocking layer without forming a void.
In a method for forming the blocking pattern using a photoresist, a photoresist film serving as a blocking layer filling the opening is formed by coating the substrate with a photoresist composition. Then, an exposure process, a developing process, a cleaning process, and a baking process are sequentially performed on the photoresist film in order to form a blocking pattern formed from photoresist. When the blocking pattern is formed from photoresist, the blocking layer is formed through a simple coating process, so it may take less time to fabricate the blocking pattern and a void may not be generated.
In order to prevent cleaning equipment from being contaminated in a subsequent cleaning process, the cleaning solution, which may be isopropyl alcohol, should not be able to dissolve the photoresist film. Further, the baking process is performed at a temperature of greater than about 270° C. in order to sufficiently cure the photoresist film so that the photoresist film will not substantially dissolve in the cleaning solution. However, a photoresist film that is cured at a relatively high temperature, like the temperature mentioned above, is not readily removed through an ashing process using plasma. As a result, a portion of the photoresist film may undesirably remain on the substrate and have a detrimental effect on the semiconductor device in which it remains. Because of the drawbacks of using polysilicon, forming the blocking pattern using photoresist is no longer a preferred method for forming the blocking pattern.
Additionally, in order to reduce the formation of cylindrical capacitor defects, an exposure process using more shots than other pattern forming processes is used to form the mold layer pattern. A defect in a capacitor may be generated when, after a lower electrode is formed, the lower electrode is shifted or removed in a subsequent process(es). To reduce such defects, the exposure process for forming the mold layer pattern is performed using a relatively high number of shots and reticle images corresponding respectively to relatively small numbers of chips.
After the lower electrode of the capacitor is formed, the wet etching process is performed to remove the mold layer pattern. In the wet etching process, the lower electrode is often shifted, pulled, or removed. In the process being described, the substrate has two main regions. One region is a central portion of the substrate, in which semiconductor chips are formed normally. The central portion of the substrate may be referred to hereinafter as a “die forming region” of the substrate. The other region of the substrate is an edge portion of the substrate, in which semiconductor chips are not formed normally. The edge portion of the substrate may be referred to hereinafter as an “edge die region” of the substrate. The edge die region is too small for a semiconductor chip to be formed in the edge die region, and the lower electrode is not formed normally in the edge die region. After an abnormal lower electrode is formed in the edge die region of the substrate, the abnormal lower electrode may be removed or shifted in a subsequent wet etching process. When an abnormal lower electrode is shifted during the wet etching process, an adjacent normal lower electrode may be affected by the shifted abnormal lower electrode and operational errors may occur.
In order to prevent a lower electrode disposed in the edge die region from being shifted or removed, the opening in which the lower electrode will be formed is formed by performing an exposure process using a reticle defining a plurality of relatively small reticle images (i.e., reticle images corresponding respectively to relatively small numbers of chips). When an exposure process for forming an opening in the edge die region is performed using a reticle defining a single reticle image that corresponds to a relatively large number of chips, an abnormal lower electrode is formed in the edge die region, which may cause a defect(s) to form in the semiconductor device. So that lower electrodes are formed only in the edge die region, the exposure process is performed using a reticle defining a plurality of reticle images in order to form openings only in the die forming region.
When the exposure process is performed using the reticle defining a plurality of reticle images, the number of chips exposed at each shot is smaller than the number of chips exposed at each shot in an exposure process using a reticle defining one reticle image. Therefore, the number of shots and the exposure time required to expose the whole substrate to light increase, which has a negative impact on manufacturing productivity. Furthermore, in order to produce a highly integrated semiconductor device and increase productivity, an expensive exposure apparatus such as an ArF scanner or a KrF scanner is used.